Implementation and Evaluation of RLS Adaptive Array Using FPGA

Recursive Least Square (RLS) is one of the algorithms that can be used to update array weights in adaptive array antennas. Although the calculation load is large, it achieves fast convergence and is thus effective under fading environments; it shows great promise in mobile communication applications [1]. We first constructed a fully functional testbed in which the RLS algorithm is implemented using Field Programmable Gate Arrays (FPGA), which are programmable integrated circuits. Then, we proposed a new architecture of systolic arrays [2] that allows a significant reduction of the number of processing clock cycles required for updating the array weights. We demonstrated that it is possible to reduce the circuit scale dramatically without impairing the processing speed by reusing circuits, making use of the symmetric property of the internal cells constituting the systolic arrays.